Browsing Researchers by Subject "VLSI"

Now showing items 1-2 of 2

    • A genetic algorithm approach to VLSI macro cell non-slicing floorplans using binary tree 

      Hasliza, A. Rahim@Samsuddin; Ab Al-Hadi, Ab Rahman; Andaljayalakshmi, G.; R. Badlishah, Ahmad; Wan Nur Suryani Firuz, Wan Arrifin (Institute of Electrical and Electronics Engineers (IEEE), 2008-05-13)
      This paper proposes an optimization approach for macro-cell placement which minimizes the chip area size. A binary tree method for non-slicing tree construction process is utilized for the placement and area optimization ...

    • High degree of testability using full scan chain and ATPG-An industrial perspective 

      Mamun, Ibne Reaz; Lee, W. F.; Hamid, N. H.; Lo, H. H.; Ali Yeon, Mohd Shakaff, Prof. Dr. (Asian Network for Scientific Information, 2009)
      This study describes an efficient design methodology from an industrial perspective on utilizing Register Transfer Level (RTL) coding style, full scan chain implementation and Automatic Test Pattern Generation (ATPG) to ...