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Electrical characterization of 0.15µm CMOS Transistor using TSUPREM-4 and MEDICI
(Universiti Malaysia Perlis, 2008-04)
Physical and electrical characteristics of 0.153m Complementary Metal Oxide Semiconductor (CMOS) were studied. Fabrications of the devices were done by
TSUPREM-4 simulator and electrical characteristics extraction will ...
Study of Semi-Recessed LOCOS for Quasi-nanoscale CMOS Device Isolation
(Universiti Malaysia Perlis, 2007-03)
This project is entitled as semi-recessed LOCOS for CMOS device isolation. Local oxidation (LOCOS) technique is a widely used method for device isolation in semiconductor process integration. It is a simple, cheap yet and ...
Design and analysis of low power using Sleepy Stack and Zig-Zag technique
(Universiti Malaysia Perlis, 2008-04)
Now days the design of CMOS becomes greater where the number of transistor in design increased largely. However there are some problem that occurs during the excellent
design and the increasing of transistor where the ...
Simulation for forming Shallow Trench Isolation in the IC using TCAD tools
(Universiti Malaysia Perlis, 2008-04)
A simulation for forming shallow trench isolation (STI) in the integrated circuit
(IC) is introduced. Firstly, using the Taurus Workbench-tools, the first silicon oxide layer and a silicon nitride layer are formed ...