Browsing School of Microelectronic Engineering (FYP) by Subject "Shallow Trench Isolation (STI)"
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Coherent effect on LOCOS and STI technique for 0.18 µm CMOS technology using Taurus Workbench
(Universiti Malaysia PerlisSchool of Microelectronic Engineering, 2008-04)LOCOS (Local Oxidation of Silicon) and STI (Shallow Trench Isolation) are two isolation techniques used in integrated circuit fabrication. Further device scaling using LOCOS technique is no longer practical for technology ... -
Simulation for forming Shallow Trench Isolation in the IC using TCAD tools
(Universiti Malaysia PerlisSchool of Microelectronic Engineering, 2008-04)A simulation for forming shallow trench isolation (STI) in the integrated circuit (IC) is introduced. Firstly, using the Taurus Workbench-tools, the first silicon oxide layer and a silicon nitride layer are formed ...