Browsing Final Year Project Papers & Reports by Subject "Multipliers (Mathematical analysis)"

Now showing items 1-4 of 4

    • 8-bits X 8-bits modified Booth 1’s complement multiplier 

      Norafiza Salehan (Universiti Malaysia PerlisSchool of Microelectronic Engineering, 2007-05)
      With advances in technology, many researchers have tried and are trying to design multipliers which offers either of following – high speed, low power consumption, regularity of layout and hence less area or even combination ...

    • Design and realization of a high Speed Multiplier Accumulator (MAC) unit for low power applications 

      Mohd Nazri Md Rejab (Universiti Malaysia PerlisSchool of Microelectronic Engineering, 2008-04)
      A fast and energy-efficient multiplier is always needed in electronics industry especially DSP, image processing and arithmetic units in microprocessors. Multiplier is such an important element which contributes substantially ...

    • High speed 8-bits x 8-bits Wallace Tree multiplier 

      Tajul Hamimi Harun (Universiti Malaysia PerlisSchool of Microelectronic Engineering, 2007-05)
      This final year project (FYP) is to analyze the design of Wallace Tree multiplier. For simplicity, unsigned operands are chosen and main focus on the short word widths commonly used in most applications: an 8-bit multiplier. ...

    • Low Power Multiplier Accumulator (MAC) unit using Sleepy Stack technique 

      Aaron Selvam Thangamany (Universiti Malaysia PerlisSchool Of Microelectronic Engineering, 2008-05)
      The main objective of this project is to provide new low power solutions for Very Large Scale Integration (VLSI) designers. Especially, the focus is on leakage power reduction. In this project, a novel circuit structure ...