Rizalafande Che Ismail, Prof. Ir. Dr.
http://dspace.unimap.edu.my:80/xmlui/handle/123456789/39253
This page provides access to scholarly publications by UniMAP Faculty members and researchers.2024-03-29T11:22:51ZHigh performance systolic array core architecture design for DNA sequencer
http://dspace.unimap.edu.my:80/xmlui/handle/123456789/69198
High performance systolic array core architecture design for DNA sequencer
Dayana, Saiful Nurdin; Mohd. Nazrin, Md. Isa; Rizalafande, Che Ismail; Muhammad Imran, Ahmad
This paper presents a high performance systolic array (SA) core architecture design for Deoxyribonucleic Acid (DNA) sequencer. The core implements the affine gap penalty score Smith-Waterman (SW) algorithm. This time-consuming local alignment algorithm guarantees optimal alignment between DNA sequences, but it requires quadratic computation time when performed on standard desktop computers. The use of linear SA decreases the time complexity from quadratic to linear. In addition, with the exponential growth of DNA databases, the SA architecture is used to overcome the timing issue. In this work, the SW algorithm has been captured using Verilog Hardware Description Language (HDL) and simulated using Xilinx ISIM simulator. The proposed design has been implemented in Xilinx Virtex -6 Field Programmable Gate Array (FPGA) and improved in the core area by 90% reduction.
Link to publisher's homepage at https://www.matec-conferences.org/
2018-01-01T00:00:00ZDevelopment of varied CMOS ring oscillator topologies in 0.13-μm CMOS technology
http://dspace.unimap.edu.my:80/xmlui/handle/123456789/34717
Development of varied CMOS ring oscillator topologies in 0.13-μm CMOS technology
Sohiful Anuar, Zainol Murad, Dr.; Rizalafande, Che Ismail, Dr.; Mukhzeer, Mohamad Shahimin, Dr.; Mohd Fairus, Ahmad; Rohana, Sapawi
This paper presents varied CMOS ring oscillator topologies using Silterra 0.13-µm Process. Three topologies of ring oscillators have been designed which is the single-ended ring oscillator, differential ring oscillator and ring oscillator based variable resistor for 2.4 GHz wireless applications. The proposed designs consist of five stages delay cell. The simulation results show that a single-ended ring oscillator obtained the lowest power consumption of 0.41 mW, while differential oscillator achieves phase noise of −64.44 dBc/Hz at 1 MHz offset frequency. However, ring oscillator based variable resistor did not achieve any significant improvement. The proposed design is oscillates at 2.4 GHz.
Link to publisher's homepage at http://www.ttp.net/
2014-01-01T00:00:00ZImproved addition and subtraction in logarithmic number system: Technique and analysis
http://dspace.unimap.edu.my:80/xmlui/handle/123456789/33539
Improved addition and subtraction in logarithmic number system: Technique and analysis
Rizalafande, Che Ismail, Dr.; Norzahiyah, Nordin; Asral, Bahari Jambek, Dr.
Logarithmic Number System (LNS) is an alternative beside Floating Point (FLP) when an application requires a large dynamic range in the number processed. It allows simple implementation of multiplication and division using a Fixed Point (FXP) method without rounding error. In contrast, LNS addition and subtraction become more complex procedure. Therefore over the year, difference ways of improving the addition and subtraction function have been purposed. In this paper several techniques have been discussed and analysed such as direct lookup table, interpolation, table partitioning and co-transformation for approximating LNS addition and subtraction.
Link to publisher's homepage at http://www.aensiweb.com/
2013-10-01T00:00:00ZA comparative analysis between logarithmic number system and floating-point ALU
http://dspace.unimap.edu.my:80/xmlui/handle/123456789/33535
A comparative analysis between logarithmic number system and floating-point ALU
Rizalafande, Che Ismail, Dr.; Coleman, John Nicholas; Norzahiyah, Nordin; Zaliman, Sauli, Dr.
The ease and accuracy of executing the multiplication and division operations by using either fixed-point addition or subtraction is what makes the logarithmic number system an attractive option. However, its main drawback is the complexity of performing addition and subtraction operations. In this paper, an analysis is carried out to compare the current state-of-the-art logarithmic number system and floating-point. The results predominantly show that the logarithmic number system offers better speed, accuracy and power-efficiency than floating-point. A new proposal for logarithmic addition and subtraction using a co-transformation method is presented, with the aim of improving its performance further.
Link to publisher's homepage at http://www.aensiweb.com/
2013-10-01T00:00:00Z