Researchers
http://dspace.unimap.edu.my:80/xmlui/handle/123456789/11679
2019-09-15T05:00:18ZElectrodeposited ZnO-nanowire/Cu2O photovoltaic device with highly resistive ZnO intermediate layer
http://dspace.unimap.edu.my:80/xmlui/handle/123456789/61801
Electrodeposited ZnO-nanowire/Cu2O photovoltaic device with highly resistive ZnO intermediate layer
Mohd Zamzuri, Mohammad Zain; Masanobu, Izaki; Ohta, Takayuki; Kondo, Misaki; Takahashi, Toshiaki; Fariza, Mohamad; Junji, Sasano; Shinagawa, Tsutomu; Pauporté, Thierry
Cl-doped ZnO-nanowire (Cl:ZnO-nws)/Cu2O photovoltaic devices were prepared by electrodeposition in aqueous solutions, and the effects of the insertion of the highly resistive ZnO (i-ZnO) layer has been demonstrated by an improvement of the photovoltaic performance. The Cl:ZnO-nws and i-ZnO layer were prepared by electrodeposition in a zinc chloride aqueous solution with saturated molecular oxygen and simple zinc nitrate aqueous solution, respectively. The i-ZnO layer was directly deposited on the Cl:ZnO-nws and suppressed the electrodeposition of the Cu2O layer on the Cl:ZnO-nws. The insertion of the i-ZnO layer between the Cl:ZnO-nws and Cu2O layers induced an improvement in the photovoltaic performance from 0.40 to 1.26% with a 0.35 V open circuit voltage, 7.1 mA•cm-2 short circuit current density, and 0.52 fill factor due to the reduction of the recombination loss.
Link to publisher's homepage at http://pubs.acs.org
2014-07-01T00:00:00ZCurrent total harmonic reduction technique on three-level single phase transformerless photovoltaic inverter using PSpice
http://dspace.unimap.edu.my:80/xmlui/handle/123456789/50186
Current total harmonic reduction technique on three-level single phase transformerless photovoltaic inverter using PSpice
Ismail, Daut; Muhammad Irwanto, Misrun; Suhelmi; Shasidharan, Gomesh Nair; Mohd Irwan, Yusoff; Muhammad Fitra, Zambak; Risnidar, Chan Bahaudin
This paper presents simulation of three-level single phase transformerless photovoltaic
inverter (TPVI). Proposed technique of the simulation is created in PSpice software. The
simulation is constructed by two voltage controlled switches, ETABLE and EVALUE block
diagram. The voltage controlled switches produce two pulse waves with difference time
delay which influence maximum voltage angle and current total harmonic distortion
(CTHD). These two voltage pulse waves are changed become three-level AC waveform by ETABLE block with magnitude of 1 V and increased by EVALUE block which following
value of photovoltaic array voltage. The output of EVALUE block is connected to AC
loads. Resistive load of 30 W lamp and inductive load of 20 W water pump are applied to
the TPVI. The result shows that maximum voltage angle which is varied from 200 to 1800
influences the CTHD, the lowest CTHD of 11.75% is obtained when the maximum voltage
angle is 1250.
Link to publisher's homepage at http://jere.unimap.edu.my
2013-01-01T00:00:00ZTracing real and reactive power in open access network
http://dspace.unimap.edu.my:80/xmlui/handle/123456789/50158
Tracing real and reactive power in open access network
Mohd Herwan, Sulaiman; Mohd Wazir, Mustafa; Omar, Aliman; Ismail, Daut
The main objective of this paper is to present a simple and general methodology for tracing the power output of each generator to the line flows and loads through out the electrical power network. The tracing algorithm is based on basic circuit theories including superposition law, equivalent current injection and equivalent impedance. After power flow solution is obtained, the contributions of individual generators are determined through the voltages, currents, power flows and losses tracing sequentially. The veracity and accuracy of the method is demonstrated by numerical examples. Comparisons of the result with previous methods are also given.
Link to publisher's homepage at http://jere.unimap.edu.my
2008-01-01T00:00:00ZEffect of stack of transformer core lamination on losses and flux distribution in 3-phase distribution transformers 1000kVa
http://dspace.unimap.edu.my:80/xmlui/handle/123456789/50157
Effect of stack of transformer core lamination on losses and flux distribution in 3-phase distribution transformers 1000kVa
Ismail, Daut; Dina Maziana, Maiz Ahmad; Shuhaimi, Zakaria; Soib, Taib
This paper describes the results of an investigation on the effect of different amount of layers per stack of core lamination in the three of 3-phase distribution transformers 1000kVA. The investigation involves the variation of power loss, building factor, total harmonic distortion of flux and flux leakages. The power loss and flux distribution have been measured using no load test in three types of model of setting of core built from the same size and type of M5 (CRGO) laminations. The power loss of the transformer core assembled with 1 layer per stack of lamination is 6.58% better than the power loss of the transformer core assembled with 2 layers per stack of lamination and is also 8.31% better than the power loss of the transformer core assembled with 3 layers per stack of lamination, at 1.5T, 50 Hz. The flux leakage at the corner joint in the core assembled with 1 layer per stack of lamination is the lowest among the three of the transformer cores, over the whole flux density range. Total harmonic distortion flux is the largest in the transformer core with 3 layers per stack of lamination and the smallest in the transformer core with 2 layers per stack of lamination. Using 1 layer per stack of lamination in transformer core is more efficient than using the other two the three lamination of the transformer core.
Link to publisher's homepage at http://jere.unimap.edu.my
2008-01-01T00:00:00Z