Please use this identifier to cite or link to this item:
http://dspace.unimap.edu.my:80/xmlui/handle/123456789/77429
Full metadata record
DC Field | Value | Language |
---|---|---|
dc.creator | Ong, Chiew Yeong | - |
dc.date | 2018 | - |
dc.date.accessioned | 2022-12-07T02:03:55Z | - |
dc.date.available | 2022-12-07T02:03:55Z | - |
dc.identifier.uri | http://dspace.unimap.edu.my:80/xmlui/handle/123456789/77429 | - |
dc.description | Master of Science Microelectronic System Design Engineering | en_US |
dc.description.abstract | In development of the die stacking interconnection technology, the thermal analysis on stacked dies are commonly engaged in semiconductor products. However, thermal issues are not the main criteria for stack die configuration and thus the combined effects of thermal and mechanical stresses are overlooked during the design of the stacked dies. As there are existence of multiple dies and other materials with different Coefficient of Thermal Expansion (CTE), thermo-mechanical loading and its effect on reliability needs to be studied for optimum the interconnection design and die configuration. The focus in this thesis is a) thermal-mechanical analysis on the wirebond interconnection of stacked die by using element analysis, b) the study of planar bonding of stacked die to improve of interconnection. The investigation is carried by modelling an Insulated-Gate Bipolar Transistor (IGBT) with wirebonds based on an investigation carried out Dudek et al. 2015. This model serves as a basis for comparison. The model undergoes cyclic heating and cooling with a temperature delta of 150K and the stress experienced by the model at the bonding interface between Wirebond and Baseplate is recorded at the of each heating and cooling cycles. The test is repeated using a model IGBT with the wirebond replaced with a planar bond, and the stress results are compared. The results of the thermal modelling matches the model by Dudek et al, showing the viability of the model. Thermomechanical analysis shows stress in the interconnection between wirebond and baseplate is highest at the edges of the interconnection and is the same for the planar bond. The results of the analysis show that the stresses in a stacked die are highest at low temperature. The planar bonding method offers a marked improvement over the wirebond in terms of interconnection stress and thus is a viable for improving the thermo-mechanical stresses in a stacked die. | en_US |
dc.language.iso | en | en_US |
dc.publisher | Universiti Malaysia Perlis (UniMAP) | en_US |
dc.rights | Universiti Malaysia Perlis (UniMAP) | en_US |
dc.subject | Insulated gate bipolar transistors | en_US |
dc.subject | Bipolar transistors | en_US |
dc.subject | Wire bonding (Electronic packaging) | en_US |
dc.subject | Planar transistors | en_US |
dc.title | Thermal-mechanical analysis of bonding pad in insulated gate bipolar transistor | en_US |
dc.type | Thesis | en_US |
dc.contributor.advisor | Vithyacharan, Retnasamy, Dr. | - |
dc.publisher.department | School of Microelectronic Engineering | en_US |
Appears in Collections: | School of Microelectronic Engineering (Theses) |
Files in This Item:
File | Description | Size | Format | |
---|---|---|---|---|
Page 1-24.pdf | Access is limited to UniMAP community. | 970.96 kB | Adobe PDF | View/Open |
Full text.pdf | This item is protected by original copyright. | 5.51 MB | Adobe PDF | View/Open |
Declaration Form.pdf | Declaration Form | 242.58 kB | Adobe PDF | View/Open |
Items in UniMAP Library Digital Repository are protected by copyright, with all rights reserved, unless otherwise indicated.