Research of large bit size superscalar pipeline VLIW microprocessor

Abstract

A microprocessor’s capability to crunch data is dependent on its bus width. The larger the bus width, the more data it can crunch at any one time. For example, the crunching capability of a 32 bit microprocessor is at a comparable doubling factor of a 16 bit microprocessor. Therefore, having a microprocessor with larger bus size allows for more data crunching capability. However there is a drawback to using larger bus size. The larger the bus size, the greater amount of logic is required, and the larger the die size. Most microprocessors in the market today such as Intel’s Xeon and EMT64 microprocessor, AMD’s Athlon 64 and Opteron microprocessor, IBM’s PowerPC microprocessor are 64 bit microprocessors. They are able to crunch data at 64 bits at a time. Moving forward, in order to have a microprocessor to have more data crunching capability, there are two methods of progress: 1. increase the bit size from 64 bits to 128/256/512 bits and beyond 2. increase the amount of microprocessor core in a single microprocessor This paper investigates into the method of hardware design to increase the bit size (128/256/512) in terms of data bus thereby allowing large chunks of data to be processed at any one time. Research results to date shows that the worst critical path when increasing the bit size is limited to adder in the ALU. This is expected as the adder forms the basic component of ALU within the microprocessor. A new adder architecture have been developed during this research that can allow for large bit size computation but yet able to provide good performance compared to all other existing adder architecture.