Algorithmic implementation to achieve high speed mathematical addition on Silicon for 128 bits and larger

Abstract

Mathematical addition is frequently used in VLSI IC design, namely in Arithmetic Logic Unit (ALU) which forms the basis of microprocessor computation core. The performance of the microprocessor is partially dependent on the performance of the ALU and the ALU is partially dependent on the performance of the adder which forms the basic computational circuit within the ALU. Therefore, to achieve high performance mathematical computation on a microprocessor, the adder must be able to perform high performance addition. With the ever increasing bit size of microprocessors, designing an adder circuit for mathematical computation of large bit size becomes an issue. This paper proposes a method to design a high speed adder circuitry using carry skip algorithm that allows for parallel computation of large bit size numbers.