The design of On-Chip high performance transformer for power IC

Abstract

A monolithic integrated transformer is proposed for power IC with two different existing transformer’s variations and configurations; namely the stacked transformer and interleaved transformer. The proposed of the on-chip transformer design is based on their best performance in the aspects of area of efficiency and cost effectiveness. This paper intends to provide discussion on the design of transformer using CADENCE software and considerations on the circuit characterization and performance estimation. The structure of the on-printed board transformer with measurement results are also presented and analyzed.