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dc.contributor.authorMadnarski Sutikno-
dc.contributor.authorUda, Hashim, Prof. Dr.-
dc.contributor.authorZul Azhar, Zahid Jamal, Prof. Dr.-
dc.date.accessioned2009-08-11T02:13:57Z-
dc.date.available2009-08-11T02:13:57Z-
dc.date.issued2007-05-
dc.identifier.citationvol.39 (5), 2008, pages 727-731.en_US
dc.identifier.issn0959-8324-
dc.identifier.urihttp://www.sciencedirect.com/science/journal/00262692-
dc.identifier.urihttp://dspace.unimap.edu.my/123456789/6796-
dc.descriptionLink to publisher's homepage at www.elsevier.comen_US
dc.description.abstractThe tunnel barriers generation and the quantum dot size shrinkage play a significant role in single-electron transistor (SET) fabrication. Because the numerically etch indicators were not found, the technical indicators, high contrast surface and high smoothness surface were used to optimize the etch process. Si nanostructures oxidation using either oxidation furnace or rapid thermal processing (RTP) equipment can result in silicon dioxide (SiO2)-embedded-Si. In this research, we compare the furnace-oxidized-Si nanostructures with the RTP-oxidized-Si nanostructures. The oxidation rate of Si nanostructures using a furnace is 0.36 nm/s, while the oxidation rate of Si nanostructures using RTP is 2.16 nm/s.en_US
dc.language.isoenen_US
dc.publisherElsevier B.V.en_US
dc.subjectPattern-dependent oxidationen_US
dc.subjectQuantum doten_US
dc.subjectRapid thermal processingen_US
dc.subjectReconstruction methoden_US
dc.subjectQuantum electronicsen_US
dc.subjectSingle-electron transistor (SET)en_US
dc.subjectTunneling effectsen_US
dc.subjectTransistors -- Design and constructionen_US
dc.titleA simple oxidation technique for quantum dot dimension shrinkage and tunnel barriers generationen_US
dc.typeArticleen_US
Appears in Collections:School of Microelectronic Engineering (Articles)
Zul Azhar Zahid Jamal, Dato' Prof. Dr.
Uda Hashim, Prof. Ts. Dr.

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