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dc.contributor.authorNormah, Ahmad-
dc.contributor.authorUda, Hashim-
dc.contributor.authorMohd Jefrey, Manaf-
dc.contributor.authorKader, Ibrahim-
dc.date.accessioned2009-08-06T12:42:30Z-
dc.date.available2009-08-06T12:42:30Z-
dc.date.issued2006-
dc.identifier.citationp.518-523en_US
dc.identifier.isbn978-1-4244-0730-9-
dc.identifier.issn1089-8190-
dc.identifier.urihttp://ieeexplore.ieee.org/xpls/abs_all.jsp?=&arnumber=4456505-
dc.identifier.urihttp://dspace.unimap.edu.my/123456789/6689-
dc.descriptionLink to publisher's homepage at http://ieeexplore.ieee.orgen_US
dc.description.abstractOverlay requirement is one of the biggest obstacles in achieving a very small feature. With the continued growth of small feature size, overlay requirement becomes tighter. Such a tight requirement requires a very high performance in alignment. Alignment performance is greatly dependent on alignment signal quality. Variation in metal deposition thickness, polishing time, and mark depth may deteriorate the alignment signals quality. In this paper, different types of alignment mark was used to evaluate the alignment performance in various process environment. Based from the findings, two grating alignment mark gives the worst alignment performance, which clearly indicates the unsuitability to use in production environment.en_US
dc.language.isoenen_US
dc.publisherInstitute of Electrical and Electronics Engineering (IEEE)en_US
dc.relation.ispartofseriesProceedings of the IEEE/CPMT International Electronics Manufacturing Technology (IEMT) Symposiumen_US
dc.subjectAlignmenten_US
dc.subjectAlignment marken_US
dc.subjectAlignment performanceen_US
dc.subjectAlignment signalen_US
dc.subjectOverlayen_US
dc.subjectIntegrated circuit technologyen_US
dc.subjectQuality controlen_US
dc.titleCharacterization of robust alignment mark to improve alignment performanceen_US
dc.typeArticleen_US
Appears in Collections:School of Microelectronic Engineering (Articles)
Uda Hashim, Prof. Ts. Dr.

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