FPGA based Twofish Algorithm

Abstract

This paper presents the architecture of Twofish algorithm implemented with field programmable gate array (FPGA). Twofish is one of the five finalists in AES contest. It is a 128-bit block cipher and can operate with variable key lengths of 128, 192 and 256 bits. This project only focused on 128 bits key length consisting of FPGA devices as the main crypto-processor and memory chip as its database unit. The input for this design is taken from the flash memory which is embedded in Altera UP3 trainer board and the output is transferred to computer by using serial interface. The algorithm is compiled and simulated using Altera Quartus II software. The result of compilation showed that the architecture consists of 35210 logic cells. The design is simulated and tested using low cost Altera Cyclone FPGA chip resulting an encryption rate of 90 Mbps when operate at 100MHz clock.