Impact of interface traps and parasitic capacitance on gate capacitance of In0.53Ga0.47As-FinFET for sub 14nm technology node

Abstract

FinFET technology has emerged to be one of the advanced nanoscale devices for Moore’s Law. The presence of several parasitic components in FinFET has significant effect on the device performance for the channel length of the order 14 nm. The III-V materials are replacing Silicon in FinFET technology to overcome the challenges faced by Silicon. The III-V compound semiconductors material such as Indium Gallium Arsenic (InGaAs), when used as channel material with high-K dielectric oxide materials faces a critical problem of interface traps. In this paper, the significance of interface traps at different energy levels was analysed in 14 nm InGaAs FinFET at high-k/InGaAs channel material. Apart from, the interface traps the gate parasitic capacitance of FinFET with channel material of InGaAs beyond 14 nm gate length was also investigated.