Enhance FIR implementation on FPGA using Systolic approach for fast processing and better throughput

Abstract

This project is about enhancing FIR filter using systolic approach for faster processing and better throughput. In signal processing, FIR filter is a filter whose impulse response is of finite duration because it settles to zero in finite time. Systolic architecture is used in this project because it will permit multiple computations for each memory access and also it can speed up the execution of compute-bound problems without increasing I/O requirements. The enhancing of FIR filter uses the Very High Speed Integrated Circuit Hardware Language (VHDL) code and the output will be displayed on the ALTERA NEEK (Nios II Embedded Evaluation Kit) board. The VHDL code plays the main role in this project. The VHDL code will be written into the Quartus software and then will be executed. The result will be displayed on the FPGA board. Finally, the performance of the design will be analysed and discussed with supervisor.