Please use this identifier to cite or link to this item:
http://dspace.unimap.edu.my:80/xmlui/handle/123456789/42079
Title: | Prototype of 16 BIT CPU on FPGA |
Authors: | Tamayanti, Ramasandram Dr Phak LenEh Kan |
Keywords: | 16 bit CPU Central Processing Unit (CPU) Central Processing Unit (CPU) -- Design and construction VHDL (Computer hardware description language) |
Issue Date: | Jun-2015 |
Publisher: | Universiti Malaysia Perlis (UniMAP) |
Abstract: | This project is about Prototype of 16 bit CPU on FPGA. This prototyping of CPU uses the Very High Speed Integrated Circuit Hardware Description Language (VHDL) and the output will be displayed on the FPGA board. Few steps are implemented in this project which is the fetch, decode, execute and store. Besides that there are few components required to develop the CPU which are the Control Unit, ALU, Storage unit, datapath and also registers. The Datapath unit and Control unit plays the main role in this project. The input will send the data and instruction in 16 bit to the registers. The VHDL code will be written into the Quartus software and then executed. The result was displayed on the FPGA board. Finally this project has successfully develop prototyping 16-bit CPU on FPGA with hardware working as per the simulation. |
Description: | Access is limited to UniMAP community. |
URI: | http://dspace.unimap.edu.my:80/xmlui/handle/123456789/42079 |
Appears in Collections: | School of Computer and Communication Engineering (FYP) |
Files in This Item:
File | Description | Size | Format | |
---|---|---|---|---|
Abstract,Acknowledgement.pdf | 138.25 kB | Adobe PDF | View/Open | |
Introduction.pdf | 113.56 kB | Adobe PDF | View/Open | |
Literature Review.pdf | 393.42 kB | Adobe PDF | View/Open | |
Methodology.pdf | 151.47 kB | Adobe PDF | View/Open | |
Results and Discussion.pdf | 415.56 kB | Adobe PDF | View/Open | |
Conclusion and Recommendation.pdf | 112.74 kB | Adobe PDF | View/Open | |
Refference and Appendics.pdf | 541.37 kB | Adobe PDF | View/Open |
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