Enhance IIR implementation on FPGA using systolic approach for fast processing and better throughput

Abstract

IIR implementation using systolic approach is for executing thickly pipelined bit parallel IIR filter are exhibited. The crucial issue of this project is system latency in sequential execution. Latency means delay between order and start to execute in sequential execution. This project is design to reduce and remove the latency during execution. Furthermore, the top level design as a block diagram to implement simple image processing system on Nios II Embedded Evaluation Kit (NEEK) board. This simple image processing system is implement with combination signal image processing module and systolic IIR filter. In addition, signal image processing module is important to combine with IIR filter to function well in a way of systolic approach. Systolic operation need to reuse input data many time to get accurate value before it is push to get perfect output. Therefore, this project achieve to enhance IIR implementation with systolic approach to get fast processing and better throughput. In conclusion, IIR get earlier stability after two round tested with simple image processing system.