Logical effort of CMOS 4-2 compressors for arithmetic circuits

Abstract

The method of Logical Effort on CMOS circuit design for speed, it is implied on a few types topologies of the 4-2 compressor. The delay is calculated with Logical Effort concept, choosing the critical path of each circuit, obtain the stage effort, delay and the transistor size for each 4-2 compressor. Software such as Mentor Graphics is chosen as software simulator, and analysis of the result. The result from the simulation is analyzed and found the delay is reduced, after optimizing by method of Logical Effort, the load of the circuit drove will determine the delay and the transistor sizing, but the method has limits. Benefits of Logical Effort on a circuit is good for initiate the ideal of design and quick hand calculations, which is lead to “time-saving” in designing a circuit that the problem designer faced, but its accuracy is limited.