Comparison of delays between 4-bits ripple-carry adder and 4-bits carry look-ahead adder using logical effort method

Abstract

In this project, two types of circuit topologies has been designed which are the 4-B its Ripple-Carry Adder Circuit (RCA) and the 4-Bits Carry Look-Ahead Adder Circuit (CLA). Delays in RCA circuit will be compared between before and after applying the Logical Effort method to determine which circuit is good in terms of having a faster response between input and output. Besides, RCA circuit also will be compared with CLA circuit to show that different circuit topologies with the same circuit function would have different circuit delays. The Logical Effort method, includessome steps such as path effort computation, best number of stages computation, minimum delay estimation, best stage effort determination and sizing the gates in the RCA circuit. In this project, after applying the Logical Effort method, the circuit will have less delays compared to the same circuit that does not apply Logical Effort, with an improvement is about 44.15%. Meanwhile, the average improvement of CLA over RCA is about 64.85% , which means different circuit topologies would have different delays. The more complex a circuit is (high fan-in) it produces more delays. Gates number did not affected the delays in a circuit which sometimes, by having addition stages with same circuit function would improved the delays and produced fast response circuit.