Please use this identifier to cite or link to this item: http://dspace.unimap.edu.my:80/xmlui/handle/123456789/40274
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dc.contributor.authorKau, Zee Shuang-
dc.date.accessioned2015-07-14T03:14:44Z-
dc.date.available2015-07-14T03:14:44Z-
dc.date.issued2011-06-
dc.identifier.urihttp://dspace.unimap.edu.my:80/xmlui/handle/123456789/40274-
dc.descriptionAccess is limited to UniMAP community.en_US
dc.description.abstractThis report presents the proper Integrated Circuit (IC) layout techniques for a parallel adder. The layout produced for this parallel adder is presented in this report. In order to design and to get a good layout, understanding on proper layout design rules and techniques are needed. The layout is designed using rules from TSMC 0.35μm CMOS technology. When designing a layout of parallel adder, layout rules such as minimum features, minimum spacing, surround, exact size, well rules, transistors rules and contact rules and specific techniques such as floorplanning, placement and routing must be followed. Parallel adder is designed by referring to the full adder. Four individual full adder cells are connected to give parallel inputs and ripple carry. The schematic and layout of the parallel adder are designed in Mentor Graphics DA and IC station. The layout has been completed design using POLY, Metal1 and Metal2 for connections. After the layout of parallel adder is finished drawn, the next steps are DRC and LVS simulation. DRC and LVS simulation are used to identify the errors which have all been faced by designer. The project with the title of A Study of Proper Integrated Circuit (IC) Layout Techniques for a Parallel Adder had been successfully.en_US
dc.language.isoenen_US
dc.publisherUniversiti Malaysia Perlis (UniMAP)en_US
dc.subjectIntegrated Circuit (IC)en_US
dc.subjectParallel adderen_US
dc.subjectCMOS technologyen_US
dc.subjectParallel adder -- Design and constructionen_US
dc.titleA study of proper integrated circuit (IC) layout techniques for a parallel adderen_US
dc.typeLearning Objecten_US
dc.contributor.advisorNorina Idrisen_US
dc.publisher.departmentSchool of Microelectronic Engineeringen_US
Appears in Collections:School of Microelectronic Engineering (FYP)

Files in This Item:
File Description SizeFormat 
Abstract, Acknowledgement.pdf333.4 kBAdobe PDFView/Open
Introduction.pdf192.35 kBAdobe PDFView/Open
Literature review.pdf192.43 kBAdobe PDFView/Open
Methodology.pdf740.23 kBAdobe PDFView/Open
Results and discussion.pdf325.15 kBAdobe PDFView/Open
Conclusion.pdf62.89 kBAdobe PDFView/Open
Reference and appendix.pdf401.36 kBAdobe PDFView/Open


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