A study of proper integrated circuit (IC) layout techniques for a parallel adder

Abstract

This report presents the proper Integrated Circuit (IC) layout techniques for a parallel adder. The layout produced for this parallel adder is presented in this report. In order to design and to get a good layout, understanding on proper layout design rules and techniques are needed. The layout is designed using rules from TSMC 0.35μm CMOS technology. When designing a layout of parallel adder, layout rules such as minimum features, minimum spacing, surround, exact size, well rules, transistors rules and contact rules and specific techniques such as floorplanning, placement and routing must be followed. Parallel adder is designed by referring to the full adder. Four individual full adder cells are connected to give parallel inputs and ripple carry. The schematic and layout of the parallel adder are designed in Mentor Graphics DA and IC station. The layout has been completed design using POLY, Metal1 and Metal2 for connections. After the layout of parallel adder is finished drawn, the next steps are DRC and LVS simulation. DRC and LVS simulation are used to identify the errors which have all been faced by designer. The project with the title of A Study of Proper Integrated Circuit (IC) Layout Techniques for a Parallel Adder had been successfully.