Simulation and design of 8-bit successive approximation analog-to-digital converter

Abstract

An analog-to-digital converter (ADC) is a device that converts an analog unit to a digital unit in order to be used with a digital device. A Successive Approximation (SAR) ADC is an ADC that constantly comparing the input voltage to the output voltage of the internal digital-to-analog converter until the best approximation is achieved. The main components of the Successive Approximation ADC are a Successive Approximation Register, a digital-to-analog converter, a shift register and a comparator. The conventional SAR ADC require the same number of clock cycle as the number of bit to fully convert the analog data to a digital data. For an 8-bit conventional Successive Approximation Register ADC, it required an 8-bit clock cycle to complete the conversion. By combining the a 4-bit Flash ADC with the 8-bit SAR ADC, the clock cycle of the ADC can be reduced by 3 clock cycle. This is because the 4-bit Flash ADC is used to obtained the 4 MSB for the ADC in 1 clock cycle and the other 4-bit of the ADC is obtained using the conventional SAR ADC hence it required only 5 clock cycle to complete the conversion instead of 8 clock cycle using the conventional method.