Subnanometer poly-silicon gap structure formation: Comparison study between size expansion and size reduction

Abstract

This study describes the comparison among the three fabrication methods of an array of poly-silicon nanogap structures. The three different methods are size expansion technique (SET), size reduction technique (SRT) and e-beam lithography (EBL) technique. Generally, SRT involves the breaking of the primarily pattern with no gap structure into nanogap scale. Conversely, SET engages in the process of enhancing the initially microgap pattern into nanogap scale. EBL refers to a lithographic process that uses a focused beam of electrons to form the circuit patterns needed for material deposition on or removal from the wafer. Using conventional photolithography, a procedure to fabricate poly-silicon nanogap structure on the wafer scale is designed. The nanogap (NG) fabrication procedure is based on the standard CMOS technology follows by employing both methods respectively. The lateral nanogap is introduced in the fabrication process using poly-silicon as an anode electrode. The similarity and distinction will be highlighted for each particular process involved in the fabrication of nanogap structures. The simple least-cost method does not require complicated nanolithography method of fabrication but it is still possible to measure the electrical properties of a single molecule. On top of that, these techniques can be applied extensively to different designs of nanogap structure down to several nanometer levels of dimensions. The innovative method reported here can easily produce a nanogap electrode in a reproducible manner.