Design and fabrication of quantum dot single electron transistors using scanning electron microscopy-based electron-beam nanolithogrphy

Abstract

Quantum dot single-electron transistor (QD SET) is a nanoscale device operated at very low temperature. To fabricate QD SET operated at room temperature, QD must be fabricated in diameter of 10 nm. QD SET promises very small integrated circuits with ultralow-power consumption. In this research, a QD SET was designed using ELPHY Quantum GDSII Editor and fabricated using top down method. The QD SET masks design consists of SET mask for source-drain formation, SET mask for point contact and SET mask for metal pad. In addition, side gate and QD were designed in the same layer as source-drain. QD SET was designed using GDSII Editor with the following dimension: source-drain (3 μm x 3 μm), QD (10-30 nm in diameter), tunnel barriers (8.365 nm in width), side gate (3 μm x 3 μm) and metal pad (20 μm x 10 μm). Silicon on insulator (SOI) was used as the starting material and e- beam lithography system was used to transfer masks patterns. Negative resist ma-N 2403 was used to fabricate source-drain, QD, side gate and metal pad. Whereas positive resist 495K PMMA was used to fabricate point contact. To fabricate QD, silicon was etched using inductively coupled plasma (ICP) etcher and its parameters were optimized. The optimum etch time is 75 s and the optimum oxygen flow rate is 28 sccm. The smallest possible QD etched using ICP etcher in this research is 63 nm. To shrink QD dimension, silicon QD was oxidized through pattern dependent oxidation (PADOX) process using rapid thermal processing (RTP) and furnace. In this research, oxidation time using RTP was optimized in the range of 5-30 s at 1000 °C. Etched silicon samples were oxidized using furnace at 1000 °C in the oxidation time range of 5-30 min. The oxygen flow rate and the nitrogen flow rate were both set at 1 l/min. SiO2-embedded-silicon was characterized using transmission electron microscopy (TEM). The dimensions of QDs in the range of 10-30 nm were achieved and the oxidation rate was optimized as well. The nano multi layers alignment was done using SEM-based e-beam lithography and platinum was used as nano mark.