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dc.contributor.authorMohd Azizi, Chik-
dc.contributor.authorUda, Hashim, Prof. Dr.-
dc.date.accessioned2012-10-21T08:11:27Z-
dc.date.available2012-10-21T08:11:27Z-
dc.date.issued2010-10-16-
dc.identifier.isbn978-967-5760-03-7-
dc.identifier.urihttp://dspace.unimap.edu.my/123456789/21495-
dc.descriptionInternational Postgraduate Conference On Engineering (IPCE 2010), 16th - 17th October 2010 organized by Centre for Graduate Studies, Universiti Malaysia Perlis (UniMAP) at School of Mechatronic Engineering, Pauh Putra Campus, Perlis, Malaysia.en_US
dc.description.abstractThis paper focuses on the comparison of the lot dispatching policies to reveal results for optimum product cycle time. The model is based on the 200mm-wafer size, 12K product Work In Progress (WIP), 10 product mixes in the current WIP with 2 new prototypes product start daily, and 3K-wafer start per week (WSPW) capacity. The dispatching policies to be compared are includes First In First Out (FIFO), Shortest Processing Time (SPT), Critical Ratio (CR), Earliest due date (EDD), Shortest Remaining Processing Time (SRPT) and Random (RAN). In the comparison, a snap shot of WIP of CMOS technology volume and product mix were taken at the wafer processing station from pad oxidation cleaning process to alloy. The result then is generated from the commercial simulation software, where requirements such as product processing time, manufacturing efficiency, equipment availability, WIP profile and product yield are the inputs for the model. The results reveal that CR dispatching policy gives the shortest cycle time for a product to complete all the processes of wafer fabrication steps compared to the other five dispatching policies by 5% to 13%. The results then enhanced and has been successfully accepted and realization in the real FAB operation.en_US
dc.language.isoenen_US
dc.publisherUniversiti Malaysia Perlis (UniMAP)en_US
dc.relation.ispartofseriesProceedings of the International Postgraduate Conference on Engineering (IPCE 2010)en_US
dc.subjectFirst In First Out (FIFO)en_US
dc.subjectShortest Processing Cycle Time (SPT)en_US
dc.subjectCritical Ratio (CR)en_US
dc.subjectEarliest Due Date (EDD)en_US
dc.subjectShortest Remaining Processing Time (SPRT)en_US
dc.subjectChemical mechanical polishing (CMP)en_US
dc.subjectFabrication (FAB)en_US
dc.subjectDays Per Mask Layer (DPML)en_US
dc.titleAnalysis of optimum dispatching policies for semiconductor fabricationen_US
dc.typeWorking Paperen_US
dc.publisher.departmentCentre for Graduate Studiesen_US
dc.contributor.urlMohd_azizi@silterra.comen_US
Appears in Collections:Conference Papers
Uda Hashim, Prof. Ts. Dr.

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