Analysis of optimum dispatching policies for semiconductor fabrication

Abstract

This paper focuses on the comparison of the lot dispatching policies to reveal results for optimum product cycle time. The model is based on the 200mm-wafer size, 12K product Work In Progress (WIP), 10 product mixes in the current WIP with 2 new prototypes product start daily, and 3K-wafer start per week (WSPW) capacity. The dispatching policies to be compared are includes First In First Out (FIFO), Shortest Processing Time (SPT), Critical Ratio (CR), Earliest due date (EDD), Shortest Remaining Processing Time (SRPT) and Random (RAN). In the comparison, a snap shot of WIP of CMOS technology volume and product mix were taken at the wafer processing station from pad oxidation cleaning process to alloy. The result then is generated from the commercial simulation software, where requirements such as product processing time, manufacturing efficiency, equipment availability, WIP profile and product yield are the inputs for the model. The results reveal that CR dispatching policy gives the shortest cycle time for a product to complete all the processes of wafer fabrication steps compared to the other five dispatching policies by 5% to 13%. The results then enhanced and has been successfully accepted and realization in the real FAB operation.