Design and implementation of fail -recover operation for embedded system based FPGA

Abstract

High speed digital systems are often applied in critical tasks or in environments where a failure can result in unacceptable malfunctions or in dangerous situations for people. This proposal presented Fail-Recover Operation unit (FROU ) design which it overcomes all the drawbacks of watchdog and fault-tolerant using an on-the-fly acquisition technique for capturing relevant system information, without adding any overhead and being completely transparent to the controlled system. The development of the system software and hardware will be totally separated from the presence of the WDP, thus dramatically simplifying the design process. All these features are easily obtained with a field programmable gate array (FPGA) implementation of the Fail Operation Recovery, so enabling a fast and straightforward design flow, reduced circuital complexity, ability to modification the design and a gain of several additional advantages.