Serial Peripheral Interface (SPI) (Front End Design)

Abstract

The Serial Peripheral Interface Bus or SPI bus is a synchronous serial data link. This device is one of ASIC design chip that have in the market. In this final year project the new form of device will be created from the beginning stage which is RTL coding. This new design will have new application rather then just an SPI. With an additional element such as FIFO, First in first out register it can be used for pipelining mechanism and also temporary storage. To start with, verilog will be selected for the hard ware description languages. Each module will start with flow chart then block diagram. After that the real coding will take place using Model sim software. Verilog coding for each part will be based on the flow chart and block diagram. Once finish its need to be tested with test bench to observe the output and performance using Model sim and Quartus2. Next is to synthesize to any kind of technology such as TSMC0.35 to study its characteristic before proceed to layout transformation. Leonardo spectrum will be used for this process. This design can be transform to any kind of technology in order to fabricate by just extracting its GDSII file.