Analysis & design low power multiplier using TSMC 0.18µm CMOS technology

Abstract

As the advance of VLSI technology, low power design has become an important topic in VLSI design. This project is to design a low power multiplier implemented in mentor graphic tools. Low power multipliers are developed through minimizing switching activities of partial product using the radix 4 booth algorithm. Before computation for two input data, the one with a smaller effective dynamic range is processed to generate booth codes, thereby increasing the probability that the partial products become zero. By employing the dynamic-range determination unit to control input data paths, the multiplier with a column-based adder tree of compressors or counters is designed. The proposed 16x16-bit multiplier reduces power consumed by the conventional multiplier. The proposed multiplier design will try to reduce the total power consumption by 20% - 30% when compared with other multiplier. The multipliers proposed herein can be broadly used in various media processing to yield low-power consumption at limited hardware cost.