16-Bits High Speed Carry Select Adder

Abstract

This report presents the design, performance evaluation of two design of 16-bit carry select adder. The layout for the high speed 16-bits carry-select adder was present in this report. The comparison of both designs is to determine a design with the high speed performance. This design approach is to minimize the carry path delay for the adder in term to get the excellent delay performance and introduced the high speed 16-bits carry select adder. The design of this carry-select adder is using the Mentor Graphic software.This software was used to implement the transistor level of this design. A simulation for this 16-bits carry select adder design has been performed using a 0.35 μm CMOS technology, and using the EZ Wave waveform viewer to analyze the delay performance. The design approach was minimizing the carry path delay using difference multiplexer. Non-modified design used the basic multiplexer as the selector of the carry, while the modified design was using the transmission gate multiplexer. The simulation results shows that the modified adder design was achieve the better speed. Waveform representations of the design were developed, and the comparable results of the delay of both design are also given. The explanations about both design and how the modified design was improved in term of the delay performance, is also discussed.