16-Bits Carry Look-Ahead Adder as a High Speed Adder

Abstract

This paper put emphasis on designing a modified carry look-ahead adder (CLA) to acquire a high speed carry look ahead in seeing as speed is the significant characteristics to a Central Processor Unit. After some historical background on this emphasize, it was found that there are several ways to increase the speed of a CLA. In this project, pipelining techniques has been carrying out. It reduces delay by multiple are overlap in execution. This project simulated its output using Quartus II software and Altera UP2 board implementation to present the speed performance of the design architectures. Using EPF10K70RC240-4 programmable family device basic CLA being constructed with XOR, AND, and OR gates. While the modified circuit uses NAND gates to replace the AND and NOT gates in CLA, it can decrease the cost of CLA and increase the speed of CLA. The CLA speed has increased to 85.47MHz from 71.94MHz and delay has decreased to 12.8ns from 15ns.