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dc.contributor.authorMohd Nasir, Ayob
dc.contributor.authorZulkifli, Md Yusof
dc.contributor.authorAsrul, Adam
dc.contributor.authorAmar Faiz, Zainal Abidin
dc.contributor.authorIsmail, Ibrahim
dc.contributor.authorZuwairie, Ibrahim, Prof. madya
dc.contributor.authorShahdan, Sudin, Dr.
dc.contributor.authorNasir, Shaikh Husin
dc.contributor.authorMohamed Khalil, Mohd Hani
dc.identifier.citationp. 49-53en_US
dc.descriptionProceeding of The 2nd International Conference on Computational Intelligence, Communication Systems and Networks (CICSyN 2010) at Liverpool, United Kingdom on 28 July 2010 through 30 July 2010. Link to publisher's homepage at
dc.description.abstractThe performance of very large scale integration (VLSI) circuits is depends on the interconnected routing in the circuits. In VLSI routing, wire sizing, buffer sizing, and buffer insertion are techniques to improve power dissipation, area usage, noise, crosstalk, and time delay. Without considering buffer insertion, the shortest path in routing is assumed having the minimum delay and better performance. However, the interconnect delay can be further improved if buffers are inserted at proper locations along the routing path. Hence, this paper proposes a heuristic technique to simultaneously find the optimal routing path and buffer location for minimal interconnect delay in VLSI based on particle swarm optimization (PSO). PSO is a robust stochastic optimization technique based on the movement and information sharing of swarms. In this study, location of doglegs is employed to model the particles that represent the routing solutions in VLSI. The proposed approach has a good potential in VLSI routing and can be further extended in future.en_US
dc.publisherIEEE Conference Publicationsen_US
dc.relation.ispartofseriesProceeding of The 2nd International Conference on Computational Intelligence, Communication Systems and Networks (CICSyN 2010);
dc.subjectBuffer insertionen_US
dc.subjectParticle swarm optimizationen_US
dc.titleA particle swarm optimization approach for routing in VLSIen_US
dc.typeWorking Paperen_US

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