Now showing items 1-2 of 2

    • A genetic algorithm approach to VLSI macro cell non-slicing floorplans using binary tree 

      Hasliza, A. Rahim@Samsuddin; Ab Al-Hadi, Ab Rahman; Andaljayalakshmi, G.; R. Badlishah, Ahmad; Wan Nur Suryani Firuz, Wan Arrifin (Institute of Electrical and Electronics Engineers (IEEE), 2008-05-13)
      This paper proposes an optimization approach for macro-cell placement which minimizes the chip area size. A binary tree method for non-slicing tree construction process is utilized for the placement and area optimization ...
    • Genetic algorithms for VLSI micro-Cell layout area optimization based on binary tree 

      Hasliza, A. Rahim@Samsuddin; Ab Al-Hadi, Ab Rahman; R. Badlishah, Ahmad; 'Aini Syuhada, Md Zain; M.I., Ahmad; Wan Nur Suryani Firuz, Wan Arrifin (ACTA Press, 2008-04-02)
      This paper presents a novel module placement based on genetic algorithm (GA) for macro-cell layouts placement that minimizes the chip area size. A binary tree method for non-slicing tree construction process is utilized ...