Fabrication and characterization of microfluidic field effect transistor on silicon substrate
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The development of a silicon-based microfluidic field effect transistor has been carried out. The main objective of this study is to present from concept, the design of a microfluidic FET and to develop its appropriate process flow in fabricating the microfluidic FET on silicon wafer, which will finally be characterized using a suitable test methodology. Hence, fabrication on a p- <100> 4 inch silicon wafer by photolithography, wet chemical etching, thermal oxidation, diffusion and metallization with focus on a liquid conduction path has been executed. A three level photo mask has been designed via AutoCAD and chrome printed on soda-lime glass. The basic structure of the device is adapted from the conventional MOSFET structure and redesigned to incorporate a liquid channel in its operation. Therefore, the functionality remains unchanged but the principal conduction path is replaced by a fluid instead of a doped semiconductor. Two reservoirs are connected via a channel with source and drain regions doped on opposite sides of the liquid channel to reduce conduction through the substrate. They are placed as far away from each other in order to minimize electron flow through the fluidic channel when not filled with fluid. The channel widths are set to five sizes, which are 5 μm, 20 μm, 50 μm, 100 μm and 500 μm in order to study the effect of the transistor characteristics against channel size. The electron mobility in the channel is significantly affected due to the presence of polar liquid. The electron drift velocity now undergoes more collisions with mobile water molecules, which is itself polar and hence affected by the applied gate electric field. The channel profiles are inspected with the aid of stylus profilometer and SEM. The capping issue of the gate on the channel i.e. a void is addressed using a thin layer of single-side aluminum coated glass glued onto the silicon surface. This however results in higher threshold voltage as the silica thickness is about 80 μm, which is much thicker than the normal MOSFET oxide. Typically the thickness of the oxide layer in MOSFET is in the range of 0.02 - 0.1μm. Therefore, this causes higher reduction in electric field at the gate area. Testing of the devices commences during the fabrication process where the various resistivity, grown layer thicknesses and other parameters are measured. However, these measurements do not give an insight towards the final device performance. Thus, an electrical test is performed on both conditions, with and without liquid inside the channel using the semiconductor parametric analyzer, curve tracer and a high current circuit. I-V characteristics and resistivity of the devices is analysed and the results show that there is some current and voltage relation and the characteristics does conform to the theory. However, the device can not be categorized either as PMOS or NMOS since the channel is undoped. The resistance is reduced by one order for wet condition as compared to dry condition. This again shows that the presence of water molecules in the channel improves the carrier mobility.