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|Title: ||High degree of testability using full scan chain and ATPG-An industrial perspective|
|Authors: ||Mamun, Ibne Reaz|
Lee, W. F.
Hamid, N. H.
Lo, H. H.
Ali Yeon, Mohd Shakaff, Prof. Dr.
|Keywords: ||Automatic test pattern generation;Design for test;DFT design methodology;Guideline;IC chip packaging;Integrated circuit;Scan chain;Sharing pin for testing;VLSI|
|Issue Date: ||2009|
|Publisher: ||Asian Network for Scientific Information|
|Citation: ||Journal of Applied Sciences, vol. 9(14), 2009, pages 2613-2618|
|Abstract: ||This study describes an efficient design methodology from an industrial perspective on utilizing Register Transfer Level (RTL) coding style, full scan chain implementation and Automatic Test Pattern Generation (ATPG) to achieve a high percentage of testability in the final Integrated Circuit (IC). The design methodology involves using an ASIC design flow with scan insertion and scan stitching performed after synthesis with scan flops set as don’t_use during synthesis process. Based on this method of ASIC design flow with the RTL coding style and guideline, an in-house 64 bit processor core that executes 3 instructions per cycle, is implemented with 0.35 micron process technology with a single scan chain of 4600 flip-flops, achieving an ATPG pattern for stuck-at at 100% test coverage and 99.81% fault coverage. Thus, creating high testability coverage with the ATPG pattern can be achieved by having a fully synchronous design using the proposed RTL coding style and full scan chain implementation. This study also describes the work around methods used when dealing with cost reduction involving reduction of test pin on the IC chip package.|
|Description: ||Link to publisher's homepage at www.ansinet.com/|
|Appears in Collections:||School of Mechatronic Engineering (Articles)|
Ali Yeon, Md Shakaff, Prof. Dr.
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