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Please use this identifier to cite or link to this item: http://dspace.unimap.edu.my:80/dspace/handle/123456789/7448

Title: A high speed and well-structured partial product generator for parallel multiplier
Authors: Rizalafande, Che Ismail
Beckett, P
???metadata.dc.contributor.url???: rizalafande@unimap.edu.my
Keywords: Multipliers (Mathematical analysis);Multiplication;Algorithms;Partial product rows
Issue Date: 2007
Publisher: Univerisiti Malaysia Perils
Citation: Journal of Engineering Research and Education, vol. 4, 2007, pages 30-40.
Abstract: Previously reported multiplication algorithms mainly focus on rapidly reducing the partial product rows down to final sums and carries used for the final accumulation. In this paper, an efficient approach for partial product generator is presented. The approach focuses on reducing the number of partial product rows by performing the two's complement operation even before applying partial products reduction techniques. Consequently, this directly influences the speed of the multiplication as well as the area of the circuits.
Description: Link to publisher's homepage at http://www.unimap.edu.my/
URI: http://www.unimap.edu.my/
http://hdl.handle.net/123456789/7448
ISSN: 1823-2981
Appears in Collections:Journal of Engineering Research and Education

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