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Please use this identifier to cite or link to this item: http://dspace.unimap.edu.my:80/dspace/handle/123456789/6888

Title: Design of 100nm single-electron transistor (SET) by 2D TCAD simulation
Authors: Amiza, Rasmi
Uda, Hashim
Awang Mat, Abd F
Keywords: Circuit simulation;Integrated circuits -- Design and construction;Single electron transistors;Transistors;Integrated circuit design;Synopsys TCAD
Issue Date: 2006
Publisher: Institute of Electrical and Electronics Engineering (IEEE)
Citation: p.367-372
Series/Report no.: Proceedings of the IEEE International Conference on Semiconductor Electronics (ICSE 06)
Abstract: One of the great problems in current large-scale integrated circuits (LSIs) is increasing power dissipation in a small silicon chip. Single-electron transistor (SET) which operate by means of one-by-one electron transfer, small size and consume very low power are suitable for achieving higher levels of integration. In this paper, SET is designed with lOOnm gate length and 10nm gate width is successfully simulated by Synopsys TCAD. The power of SET device that obtained from simulation is 3.771 x 10-9 Watt for fixed current and 3.3565 x 10-9 Watt if fixed the gate voltage, VG, and the capacitance of this device is 0.4297 aF. These results were achieved at room temperature operation.
Description: Link to publisher's homepage at http://ieeexplore.ieee.org
URI: http://ieeexplore.ieee.org/xpls/abs_all.jsp?=&arnumber=4266633
http://hdl.handle.net/123456789/6888
ISBN: 0-7803-9730-4
Appears in Collections:School of Microelectronic Engineering (Articles)
Uda Hashim, Prof. Dr.

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