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Please use this identifier to cite or link to this item: http://dspace.unimap.edu.my:80/xmlui/handle/123456789/6885

Title: The performance study of two genetic algorithm approaches for VLSI Macro-Cell layout area optimization
Authors: Hasliza, A. Rahim @ Samsuddin
Rahman, A. A A
R. Badlishah, Ahmad
Wan Nur Suryani Firuz, Wan Ariffin
Muhammad Imran, Ahmad
Keywords: Integrated circuit layout;Genetic algorithms;Logic design;Trees (mathematics);Very large scale integrated (VLSI);Circuit optimisation;Integrated circuits;Integrated circuits -- Design and construction
Issue Date: 2008
Publisher: Institute of Electrical and Electronics Engineering (IEEE)
Citation: p.207-212
Series/Report no.: Proceedings of the 2nd Asia International Conference on Modeling & Simulation (AICMS 08)
Abstract: Very large scale integrated (VLSI) design has been the subject of much research since the early 1980s where the VLSI cell placement emerges to be a crucial stage in the chip design. Its area optimization is very important in order to reduce the delay and include more functionalities to the designed chip. The VLSI cell area optimization continues to become increasingly important to the performance of VLSI design due to the accelerating of the design complexities in VLSI. Thus, this paper addresses the performance comparisons of two different types of genetic algorithm (GA) techniques for VLSI macro-cell layout area optimization by utilizing the adopted method of cell placement that is binary tree method. Two GA approaches which are simple genetic algorithm (SGA) and steady-state genetic algorithm (SSGA) have been implemented and their performances in converging to their global minimums are examined and discussed. The performances of these techniques are tested on Microelectronics Center of North Carolina (MCNC) benchmark circuit's data set. The experimental results demonstrate that both algorithms achieve acceptable area requirement compared to the slicing floorplan approach (Lin et al., 2002). However, SSGA outperforms SGA where it achieves faster convergence rate and obtains more near optimum area.
Description: Link to publisher's homepage at http://ieeexplore.ieee.org
URI: http://ieeexplore.ieee.org/search/wrapper.jsp?arnumber=4530477
http://hdl.handle.net/123456789/6885
ISBN: 978-0-7695-3136-6
Appears in Collections:School of Computer and Communication Engineering (Articles)
R. Badlishah Ahmad, Prof. Dr.

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