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Please use this identifier to cite or link to this item: http://dspace.unimap.edu.my:80/xmlui/handle/123456789/6796

Title: A simple oxidation technique for quantum dot dimension shrinkage and tunnel barriers generation
Authors: Madnarski Sutikno
Uda, Hashim, Prof. Dr.
Zul Azhar, Zahid Jamal, Prof. Dr.
Keywords: Pattern-dependent oxidation;Quantum dot;Rapid thermal processing;Reconstruction method;Quantum electronics;Single-electron transistor (SET);Tunneling effects;Transistors -- Design and construction
Issue Date: May-2007
Publisher: Elsevier B.V.
Citation: vol.39 (5), 2008, pages 727-731.
Abstract: The tunnel barriers generation and the quantum dot size shrinkage play a significant role in single-electron transistor (SET) fabrication. Because the numerically etch indicators were not found, the technical indicators, high contrast surface and high smoothness surface were used to optimize the etch process. Si nanostructures oxidation using either oxidation furnace or rapid thermal processing (RTP) equipment can result in silicon dioxide (SiO2)-embedded-Si. In this research, we compare the furnace-oxidized-Si nanostructures with the RTP-oxidized-Si nanostructures. The oxidation rate of Si nanostructures using a furnace is 0.36 nm/s, while the oxidation rate of Si nanostructures using RTP is 2.16 nm/s.
Description: Link to publisher's homepage at www.elsevier.com
URI: http://www.sciencedirect.com/science/journal/00262692
http://hdl.handle.net/123456789/6796
ISSN: 0959-8324
Appears in Collections:School of Microelectronic Engineering (Articles)
Zul Azhar Zahid Jamal, Prof. Dr.
Uda Hashim, Prof. Dr.

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