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|Title: ||Low power reconfigurable sub-band filter bank ASIC for MP3 decoder|
|Authors: ||Gangamamba, B. P.|
Muralidhar, Pendyala V.
Murthy, Nukala Satyanarayana
|Keywords: ||Low power reconfigurable pipelined architecture;MP3 decoder;Single precision multiplier;Synthesis filter banks|
|Issue Date: ||2009|
|Publisher: ||Inderscience Publishers|
|Citation: ||International Journal of Information and Communication Technology, vol. 2 (1/2), 2009, pages 156-165|
|Abstract: ||There is an ever demanding need to develop low power audio devices using MP3 technology. From the profiled results of MP3 algorithm on ARM processors, it has been observed that the synthesis filter bank in the audio decoder consumes maximum power. Hence, to reduce the power consumption of the filter bank, we developed an IEEE 754 single precision floating-point runtime reconfigurable architecture. The proposed architecture consumes less power at run time as the last 12 bits of the mantissa part of the synthesis filter coefficients are zero most of the time and, hence, the corresponding multipliers will be switched off. Since the active multipliers during inverse polyphase quadrature mirror filter banks (IPQMF) are less, we are able to achieve low powered decoding process without significantly compromising on the accuracy and speed. We synthesised and simulated the architecture using 0.35 m process technology under synopsys environment. A uniform worst case power reduction of 23.7% has been achieved in the frequency range from 1 MHz to 20 MHz when all the multipliers are in active state.|
|Description: ||Link to publisher's homepage at http://www.inderscience.com/|
|Appears in Collections:||School of Computer and Communication Engineering (Articles)|
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