iRepository at Perpustakaan UniMAP >
UNIVERSITY LIBRARY >
Conference Papers >
Please use this identifier to cite or link to this item:
|Title: ||New QC-LDPC codes implementation on FPGA platform in Rayleigh fading environment|
|Authors: ||Farid, Ghani, Prof. Dr.|
Abid, Yahya, Dr.
|Keywords: ||Bit error rate|
|Issue Date: ||20-Feb-2011 |
|Publisher: ||Institute of Electrical and Electronics Engineers (IEEE)|
|Citation: ||p. 206-210|
|Series/Report no.: ||Proceedings of the IEEE Symposium on Computers and Informatics (ISCI 2011)|
|Abstract: ||This paper presents performance of Quasi-Cyclic low-density parity-check (QC-LDPC) codes on a flat Rayleigh fading channels by employing DPSK modulation scheme. The BER curves show that large girth and diversity level robust the system performance. Moreover, Prototype architecture of the LDPC codes has been implemented by writing Hardware Description Language (VHDL) code and targeted to a Xilinx Spartan-3E XC3S500E FPGA chip. Simulation results show that the proposed QC-LDPC codes achieve a 0.1dB coding gain over randomly constructed codes and perform 1.3 dB from the Shannon-limit at a BER of 10-6 with a code rate of 0.89 for block length of 1332.|
|Description: ||Link to publisher's homepage at http://ieeexplore.ieee.org|
|Appears in Collections:||Conference Papers|
Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.