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Please use this identifier to cite or link to this item:
http://hdl.handle.net/123456789/11392
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| Title: | Implementation of 128/256 bit data bus microprocessor core on FPGA |
| Authors: | Weng, Fook Lee
Ali Yeon, Md. Shakaff, Prof. Dr. |
| E-mail: | seanlee@emersysdesign.com
aliyeon@unimap.edu.my |
| Keywords: | Large data bus size microprocessor
VLIW
FPGA |
| Issue Date: | May-2007 |
| Publisher: | International Congress for global Science and Technology (ICGST) |
| Citation: | Journal of Programmable Devices, Circuits, and Systems, vol.7(1), 2007, pages 7-13 |
| Abstract: | This paper shows the implementation of a large data
bus size microprocessor core of 128/256 bits on an
Altera Stratix 2 FPGA using a superscalar
architecture of 3 parallel pipes with 4 stage pipeline
as shown in Figure 1. The system level
implementation utilizing the implemented
microprocessor core on FPGA is shown in Figure 2.
The micro-architecture of the microprocessor core
architecture of Figure 1 is implemented using four
pipe stages of fetch, decode, execute and writeback
with a shared register file for all 3 parallel pipes, as
shown in Figure 3. |
| Description: | Link to publisher's homepage at http://www.icgst.com |
| URI: | http://www.icgst.com/pdcs/Volume7/Issue1/PDCS0712001.pdf
http://hdl.handle.net/123456789/11392 |
| Appears in Collections: | Ali Yeon, Md Shakaff, Prof. Dr.
School of Mechatronic Engineering (Articles)
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