Now showing items 1-2 of 2

    • Taguchi Method for p-MOS threshold voltage optimization with a gate length of 22nm 

      Izwanizam, Yahaya; F. Salehuddin; K. E. Kaharudin; A. H. Afifah Maheran (Universiti Malaysia Perlis (UniMAP), 2023-01)
      This paper describes the virtual design of a 22nm gate length p-type metal oxide semiconductor, PMOS. Silvaco, TCAD tools were used to fabricate the device design and to characterize the device’s electrical properties. ...
    • Virtual fabrication of 14nm gate length n-Type double gate MOSFET 

      N. H. N. M. Nizam; F. Salehuddin; K. E. Kaharudin; Noor Faizah Z. A (Universiti Malaysia Perlis (UniMAP), 2023-01)
      Due to Moore's law, it is that predicted the channel length of a metal-oxide-semiconductor Field Effect Transistor (MOSFET) will tend to shrink from the submicron to the nanoscale size. Thus, precision in the manufacturing ...